The present technology relates to a data transfer circuit, an imaging device and an imaging apparatus, and, particularly, to a data transfer circuit, an imaging device and an imaging apparatus which can suppress an increase in transfer delay.
In the related art, there is an imaging device which performs A/D conversion in pixel signals that are read from pixel array for each line, respectively and transfers the pixel signals to a data output section. In such an imaging device, there is a concern that a difference between a delay time of the pixel signals which are read from a pixel column of a far side from an output side and a delay time of the pixel signals which are read from a pixel column of a near side from the output side is large, a setup time margin and a hold time margin of a flip-flop measuring synchronization with a global clock are reduced and a transfer speed is decreased in a data transfer circuit which transfers the pixel signals.
Then, a data transfer circuit is considered which performs data capture in a digital data output section with high accuracy at a high speed by reducing delay generated in a transfer line through which the data is transferred to the digital data output section by adjusting the delay of a clock line for the data capture of the digital data output section (see, for example, Japanese Unexamined Patent Application Publication No. 2008-306695).